Researcher
IDLab-imec
Dec 2020 / Feb 2021 - Present
Full time
Paid
Affiliated with Ghent University, University of Antwerp and imec
Antwerp, Belgium
Neutron Beam User
Rad-Hard
Embedded AI
Dec 06, 2023 - Dec 11, 2023
Oxford, UK
- Collaborated with experienced users (Prof. Paolo Rech and Dr. Fernando Fernandes) to setup experiments in the beam room
- Tested the reliability of embedded AI, namely, Neural Networks (NN) and Hyperdimensional computing (HDC) algorithms with Nordic nRF52840 DK (ARM Cortex-M4) against soft-errors
- Acquired data from the radiation experiments
- Adapted for the exprimental facility’s infrastructure and improved beam usage efficiency with on-the-spot code/setup development
- Enjoyed the networking opportunities with other users
Research Intern
TIMA
Nov 07, 2022 - Dec 05, 2022
French mobility grant
Grenoble, France
- Acquired data from previous radiation experiments
- Developed error analysis script for analysing the acquired data
- Explored the possibility of future publications based on the findings
- Enjoyed the networking and exposure to new collaboration opportunities
- Strengthened our existing collaboration with TIMA
- French mobility grant: The research stay was funded under the program ‘Bourse de mobilité Génération IA 2030’
Project Associate
IIT-M
Jul 2019 - Nov 2020
Full time
Paid
Chennai, India
- Developed an in-order 5 stage RISC-V processor’s cycle-accurate model with GEM5 simulator using C++, Python, hexedit, GDB, RISCV-GNU toolchain and Git
- Developed, reviewed and ported RISC-V ISA compliance tests for the RISCOF framework using RISC-V assembly language
- Supervised interns and guided them in porting compliance tests for RISCOF framework
- Publication: RISC-V CPU model named ProtoCPU at RISC-V global forum, 2020
Research and Project Intern
IIT-M
Nov 11, 2018 - Feb 11, 2019
Chennai, India
- Developed more than 20 compliance tests for RISC-V privileged ISA specification with SHAKTI team which helped in detecting a bug within the RTL design of processor IP core
- Enjoyed the continuous learning process in the dynamic environment
- Languages: RCISC-V assembly language, GNU make
- Tools: Git, RISC-V ISA specifications, Spike ISS, RISCV-GNU toolchain
Intern
May 2018
Bangalore, India
- Designed and simulated a complete harness test system with embedded C using Atmel Studio, Proteus EDA, Atmega328p
- Explored the satellite development phases in ISAC (ISRO satellite centre)
- I enjoyed the planning phase
Intern
Dec 19, 2016 – Jan 17, 2017
Chennai, India
- I enjoyed the planning phase
- Studied the function of voltage regulator modules (VRM) in motherboard using a D945GCCR motherboard, Arduino and Oscilloscope
- I enjoyed working with the PWM pulses and Datasheets
Summer Intern
May 2, 2016 – Jun 24, 2016
Full time
Paid
Bangalore, India
- Modeled a minimum viable product (MVP) based on gaming for the product development team to rectify the ‘help’ problem with their software support system
- I enjoyed their hospitality.